L9 – VHDL Overview VHDL Overview Rules for State Assignment Application of rule Gate Implementation Ref: text Unit 15.8 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne DeGroat, ECE, OSU 2 Overview HDL – Hardware Description Language A language that allows description of hardware for documentation, simulation, synthesis, verification, … To use an HDL you need a CAD system that supports it. Major CAD systems support VHDL, Verilog, System C, System Verilog CAD systems…
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