Queen Mary, University of London

VHDL for synthesis
ECS617
Mahamed Abdilahi Qaalib
3/28/2014

Exercise 1
Aim: To compare the results of different architectural descriptions for the same entity
Timing path analysis

Logic
Route
Total

EXERCISE 1A
7.567 ns
3.081 ns
10.648 ns

EXERCISE 1B
7.567 ns
3.081 ns
10.648 ns

EXERCISE 1C
7.567 ns
3.081 ns
10.648 ns

EXERCISE 1A
5.00 sec

EXERCISE 1B
5.00 sec

EXERCISE 1C
5.00 sec

5.14 sec

5.20 sec

5.13 sec

255924 kilobytes

255860 kilobytes

255476 kilobytes

Real & CPU time summary

Total REAL time to Xst completion Total CPU time to Xst completion Total memory usage

Utilisation summary

From the device utilization results table shown above we can see that the number of slices in all three synthesis are 2 out of 768 (0%), likewise with the 4 input LUTs. Synthesis tools find the best solution with these fairly simple codes.
The timing path analysis also illustrates that they all have the same values in both logic and route times. But the Real and CPU time to Xst completion suggest otherwise with slightly different values.
The RTL designs shown below also illustrates they are all the same component wise.

1

Fig. 1 RTL design of all Ex. 1-3

Fig. 2 RTL design of all Ex. 1-3 (top view)

Exercise 2
Aim: To illustrate the use of “don’t care” values in synthesis
Timing path analysis

Logic
Route
Total

Do care
7.016 ns
1.941 ns
8.957 ns

Don’t care
7.016 ns
1.941 ns
8.957 ns

Utilisation summary

2

Real & CPU time summary

Total REAL time to Xst completion Total CPU time to Xst completion Total memory usage

Do care
5.00 sec

Don’t care
5.00 sec

5.35 sec

5.30 sec

255348 kilobytes

254964 kilobytes

Fig. 3 RTL design of docare.vhd and dontcare.vhd
Comparing report files for these two designs illustrates that they both have same building blocks.
Hence their device utilization and their combinational path delay of 8.957 ns is the same. The only difference here being their CPU time to Xst completion, this is because in “docare.vhd” takes longer and goes through all steps computing the output where as “dontcare.vhd” doesn’t care as its name suggest to go through those steps.

Exercise 3
Aim: To illustrate logic resources requirements for conditional versus mutually exclusive input conditions Utilisation summary
Logic utilisation

Used
Available
Usage
Conditional Exclusive Conditional Exclusive Conditional Exclusive
3
2
768
768
0%
0%

Number of Slices
Number of 4 input LUTs

5

4

1536

1536

0%

0%

Number of bonded IOBs

7

7

124

124

5%

5%

The utilisation summary above illustrates that conditional uses more number of slices and one more
4 input LUTs. Therefore conditional use more resources.
3

Timing path analysis
Conditional
7.210 ns
2.487 ns
9.697 ns

Logic
Route
Total

Exclusive
7.210 ns
2.487 ns
9.697 ns

Real & CPU time summary

Total REAL time to Xst completion Total CPU time to Xst completion Total memory usage

Conditional
6.00 sec

Exclusively
5.00 sec

5.83 sec

5.55 sec

256308 kilobytes

255156 kilobytes

The conditional is slower than the mutually exclusive because it executes a sequence of statements those sequence depends on one condition. Each condition is checked until a true is found.
Place and route level

Source pad a b c d j k

Pad to Pad
Destination pad
Conditional
Delay (ns) x 7.775 x 7.895 x 7.926 x 7.716 x 6.872 x 7.582

Exclusive
Delay (ns)
7.775
7.895
7.926
7.716
6.872
7.582

Exercise 4
Aim: To review resources and timing requirements of a complex reset function

Fig. 4 Reset timing diagram of cntpt.vhd (Asynchronous)

4

Fig.5 Reset timing diagram of cntpt2.vhd (Synchronous)
Examining the two reset timing diagrams (Fig. 4-5)above shows that when reset signal is applied in the first case and