ASSIGNMENT SUBMISSION &
FEEDBACK
School: Architecture, Computing & Engineering
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BENG HONS Electrical and Electronic
Engineering

Embedded Systems and IC Design
EE3003
Andrew Chanerley

Assessment Deadline: 08/May/2013
Assessment :
Component Number: 001
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I confirm that no part of this assignment, except where clearly quoted and referenced, has been copied from material belonging to any other person e.g. from a book, handout, another student. I am aware that it is a breach of UEL regulations to copy the work of another without clear acknowledgement and that attempting to do …show more content…
This is because there are no carries that need to propagate/”ripple” through each stage.
This is clearer from the following calculation:
Carry Bit (4)
+
Sum
Carry Bits 1

Bit 3
1
1
0

Bit 2
0
1
1

Bit 1
0
1
1

Bit 0
1
0
1

Decimal
9
14
23 (including the carry bit)

From this we can see that only bit 3 produces a carry.
Due to this the final answer is obtained in the first iteration.
For the second input, 0xD16 + 0xB16, the output (fig. 4.2) is also the correct result as expected.

7

Figure 4.2 – Output waveform of 4-bit adder VHDL code for 0xD16 + 0xB16 = 0x18
Due to the reduced propagation delays, the output is now obtained after 75 ns.
For the final input, 0110B + 0111B, a similar situation to the first input occurs.

Figure 4.3 – Output waveform of 4-bit adder VHDL code for 0110B + 0111B = 1101B
The output is obtained earlier, than expected (after 75 ns), namely at 65 ns (see fig. 4.3).
This is due to there being no carries that need to propagate/”ripple” through for every stage.

Carry Bit (4)
+
Sum
Carry Bits 0

Bit 3
0
0
1
1

Bit 2
1
1
1
1

Bit 1
1
1
0

Bit 0
0
1
1

Decimal
6
7
13 (including the carry bit)

8

The only carries that need to propagate occur at the last stage, as seen in above calculation.
The system therefore only needs 2 iterations to obtain the right result. One iteration to produce the
carries