Introduction to Micro- and
Nano-fabrications
ECE440

Nanoelectronics

Zheng Yang
(e-mail: yangzhen@uic.edu; ERF3017)

Department of Electrical & Computer Engineering
University of Illinois at Chicago

The first transistor:
Bell Labs,
December 23, 1947

Excellent reference:
Hans Queisser, The
Conquest of the Microchip,
Harvard University Press,
1988
Page 2

Integrated Circuit Manufacture

0.75 micron dielectric features
Integrated circuit 1992-1998

0.18 micron dielectric features
Integrated circuit 1998-2000
Page 3

Moore’s Law Example: Size/complexity
Historical trend and SIA roadmap projections 1994….
Historical Trend
Industry Roadmap

Dimension (micron)

20 
10.0

4.4 
1.2 

1.0

0.35 
0.25 
0.18 
0.13 
0.10 
0.07 

0.1
1960

1970

1980

1990

2000

2010
Page 4

Technologies Involved in
Micro- and Nanofabrications

Page 5

Single crystal silicon ingots are produced with a crystal pulling process called the CZ (Czochralski) method.
Crushed high-purity polycrystalline silicon is doped with elements like boron or phosphorous and melted at
1400° in a quartz crucible surrounded by an inert gas atmosphere of highpurity argon. The melt is cooled to a precise temperature, then a "seed" of single crystal silicon is placed into the melt and slowly rotated as it is
"pulled" out.

Page 6

Ingot Characterization
Single crystal silicon ingots are characterized by the orientation of their silicon crystals. Before the ingot is cut into wafers, one or two "flats" are ground into the diameter of the ingot to mark this orientation. Wafer Slicing
After characterization, wafer producers
(Komatsu Silicon America, MEMC,
Mitsubishi Silicon America) slice the ingot into individual wafers with a precision "ID
Saw“( so named because the cutting edge of the blade is on the inside) or a wire saw.
You only need the surface of the semiconductor; the thinner the slice the more efficient the process.
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Wafer Polishing
Next, the wafers are polished in a series of a combination chemical and mechanical polishing processes. The wafers are held in a hard ceramic chuck using either wax bonding or vacuum and buffed with a slurry of silica powder, DI water and sodium hydroxide.
The polishing process usually involves two or three polishing steps with progressively finer slurry and intermediate cleanings using RO/DI water.
Page 8

The purpose of EPI growth is to create a layer with different, usually lower, concentration of electrically active dopant on the substrate. For example, an n-type layer on a ptype wafer.

Page 9

Oxidation Layering.
Oxidation layering produces a thin layer of silicon dioxide, or oxide, on the substrate by exposing the wafer to a mixture of highpurity oxygen and hydrogen at ± 1000°C (1800°F).
Oxide is used to provide insulating and passivation layers and to form transistor gates. Insulating oxide layers are usually about ± 1500 Å.
Gate layers are usually between below 200 Å.
Page 10

Photoresist Coating.
Photoresist is a photo-sensitive material applied to the wafer in a liquid state in small quantities. The wafer is spun at ca. 3000 rpm which spreads the "puddle" into a uniform layer between 2 and 200 µm thick.

Page 11

Lithographic Exposure.
A lithographic exposure tool exposes a photoresist coated wafer UV light passing through a reticle which contains the image of a single device layer. Many exposure tools are termed "steppers" because of the "step-and-repeat" action of moving the wafer on its x and y axes to align the reticle with each individual device position.
UV light is used because modern semiconductor device features are so small that the actual wavelength of the exposing light is a limiting factor.
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Develop and Bake.
After exposure, wafers are developed in either an acid or base solution to remove the exposed areas of photoresist.
Once the exposed photoresist is removed, the wafer is "softbaked" at a low temperature to harden the remaining photoresist.

Page 13

Acid Etch and Strip.