Very Long Instruction ( VLIW ). And multi-threaded have a wide application es[specially in speed improvement. But each architecture has its own features and there is a significant difference between them. Processing, and experience in low-level programming of microprocessors. Advanced microprocessors with instruction-level parallelism, e.g., superscalar and very long instruction word (VLIW) computer architectures, but also how to analyze and efficiently map various image and video computing algorithms on these microprocessors. Every
VLIW processor tries to utilize both instruction-level and data-level parallelism. They
Distinguish between themselves in the number of banks and amount of on-chip memory and/or
Cache, the number and type of functional units, the way in which the global control flow is
Maintained, and the type of interconnections between the functional units.
Introduction
The purpose of this project is to discuss the characteristics, and advantages of the Very Long
Instruction (VLIW). And multi-threaded, Multiple instruction issue (superscalar). In this new technology scientist is concerned how to improve Architectural Innovations for Improved
Performance. Computer performance grew by a factor of about 10000 between 1980 and 2000,
100 due to faster technology, and 100 due to better architecture. We should look at establish, factors, and improvement methods.
.
VLIW is defined by Very Long Instruction Word. It combined several bits instructions or one word; VLIW has the capability to to read several instructions. Reading and Execution can be performed in parallel instructions/
If we have word length=48, we can add to it several increments, and execution can be performed in the same time under consolidations.
VLIW designers have a few basic choices to make regarding
Architectural rules for register use. Suppose a VLIW is designed with self-drainPipelines: once an operation is initiated, its results will appear in
The destination registers at most L cycles later (where L is the latency of the operaTin). There are never enough registers, so there is a temptation to wring maxiMum use out of the registers that exist. Consider. If loads have a 1 +
2 cycle latency, unroll this loop once, and show how a VLIW capable of two
Loads and two adds per cycle can use the minimum number of registers, in the
Absence of any pipeline interruptions or stalls. Give an example of an event that,
In the presence of self-draining pipelines, could disrupt this pipelining and yield
VLIW has a good latency of operation to initiate the results to appear at certain destination
For the required register. VLIW has the capability for 2 loads and 2 Cycle+1 latency. This feature helps to reduce the number of register. However if the pipeline interruption has a halt there will be disruption for the pipelining
“With an endowment of $650M, the future of IAS is more or less assure” Bhrooz Parhami IAS
RSX-11 is a family of real-time operating systems mainly and IAS was a time-sharing version of
RSX-11
A VLIW is a processor that can process in parallel several individual and very simple instructions that have been put together into one long word unlike a non-VLIW processor which can only process a single instruction at a time
Advantages
Parallel execution can be easily detected at several periods or intervals to perform several executed instructions’ Different ALU instructions are usually packed together to execute instructions. Compiler execute them in parallel
Very long instruction word or VLIW refers to a processor architecture designed to take advantage of (ILP). Whereas conventional processors mostly only allow programs that specify instructions to be executed one after another, a VLIW
