International Journal of Computer Applications (0975 – 8887)
Volume 96– No.18, June 2014

Design of High Speed Full Adder using Improved
Differential Split Logic Technique for 130nm Technology and its Implementation in making ALU
Gurleen Kaur
Mtech Microelectronics
UIET, Panjab University
Chandigarh, UT India

Arvind Kumar
Assistant Professor, ECE
UIET, Panjab University
Chandigarh, UT India

ABSTRACT
Adders are the main components in digital designs which are used not only for addition but can be used for multiplication and division too. Adders find use in very large scale integrated circuits from processors (like in arithmetic logic circuits) to application specific integrated circuits. At the same time, high speed computation has become the important part of any digital applications today though low power is a key factor too. In this paper, a high speed full adder using improved differential split logic (DSL) technique is used. We further implement it in 1bit arithmetic logic circuit (ALU).
Measurements show that proposed full adder is better than
DSL full adder in terms of speed, and further implementation of it in ALU shows that it is better than CMOS ALU in terms of speed, power and power delay product (PDP).

General Terms
Full adder, Differential split level logic (DSL), Differential cascade voltage logic (DCVS), Arithmetic logic circuit
(ALU), Power delay product (PDP), Full adder (FA),
Multiplexer (Mux).

Keywords
Differential Split logic, Full adder, Arithmetic logic circuits

1. INTRODUCTION
Full adders are the heart of all arithmetic calculations [13]. It is a combinational logic unit that performs all the calculations like addition, subtraction, increment and decrement. There are certain factors that can simply slow down the development of small complex IC chips. These factors are design cost, design productivity and IC fabrication technology. The increasing demand for high speed very large scale integration can be obtained at design levels such as architectural, circuit and layout level .For the circuit design, at this level a proper choice of logic design style for high speed combinational logic circuits should be done. It is because all the important parameters affecting speed are switching capacitance, transition activity and short circuit currents are actually influenced by the chosen logic style. Earlier the parameters like power dissipation, small area and cost factor were given more weight age , but now days speed considerations are also the important factors for the scientific community related to
VLSI designs.
In CMOS technology, even if we design high speed full adder, power dissipation is also taken care of. Power dissipation is one of the critical factors which is of two types and is classified into dynamic power and static power. Dynamic power dissipation comes into picture when the circuit is

Jatinder Singh
Assistant Professor, ECE
UIET,Panjab University
Chandigarh,UT India

operational and static power dissipation is considered when the circuit is inactive.
Dynamic power is further classified into switching power
(Pswitch) and short circuit power (Psc).Static power is because of leakage power dissipation [7].
There are three major sources of power dissipation which are given in the following equation.

Ptotal   .Cl .Vdd . f clk  I sc .Vdd  I leakage.Vdd
2

The first term shows the switching component of power where α is the switching factor, Cl is the loading capacitance, fclk is the clock frequency. The second term represents the dissipation due to short circuit currents. The last term is the dissipation due to leakage currents ( Ileakage )[1].
The switching power dissipation in CMOS digital integrated circuits is an important function of the power supply voltage
Vdd Reduction of power supply voltage is an important way to limit the power dissipation. But then limiting the power dissipation, results in increased circuit delay. The given equation tells about the dependence of delay on power